webPic
PHONE

Office: 264

EMAIL

kalam@ewubd.edu

Dr. Khairul Alam

Professor
Department of Electrical & Electronic Engineering

PhD in Electrical Engineering, University of California, Riverside, USA
MSc in Electrical Engineering, BUET, Bangladesh
BSc  in Electrical Engineering, BUET, Bangladesh

August 26, 2012 – August 25, 2014 : Postdoctoral research fellow, The University of Tokyo, Japan.

June 26, 2006 – September 15, 2006 : Intern co-op, IBM T. J. Watson Research Center at Yorktown Heights, New York, USA.

September 2003 – December 2006 : Research Assistant, LAboratory for Terascale and Terahertz Electronics (LATTE), University of California, Riverside, USA.

  • Electron transport in semiconductor nanostructures
  • Strain engineering for improved performance of nano transistors
  • Photovoltaics and solar cell
  • Electronics of 2D materials

Journal Publication

  1. Somaia S. Sylvia, Khairul Alam, and Roger Lake, Uniform Benchmarking of Low-Voltage van der Waals FETs,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 2, pp. 28-35, October 2016.
  2. Kalyan Mondol, Md. Manzurul Hasan, Yeasir Arafath, and Khairul Alam, “Quantization effects on the inversion mode of a double gate MOS,” Results in Physics, vol. 6, pp. 339-341, June 2016.
  3. Khairul Alam, Shinichi Takagi, and Mitsuru Takenaka, “A Ge ultrathin-body n-channel tunnel FET: Effects of orientation,” IEEE Transactions on Electron Devices, vol. 61(11), pp. 3594-3600, November 2014.
  4. Somaia S. Sylvia, K. M. Masum Habib, M. Abul Khayer, Khairul Alam, Mahesh Neupane, and Roger Lake, “Effects of random, discrete source dopant distribution on nanowire tunnel FETs,” IEEE Transactions on Electron Devices, vol. 61(6), pp. 2208-2214, June 2014.
  5. Khairul Alam, Shinichi Takagi, and Mitsuru Takenaka, “Strain-modulated L-valley ballistic-transport in (111) GaAs ultrathin-body nMOSFETs,” IEEE Transactions on Electron Devices, vol. 61(5), pp. 1335-1340, May 2014.
  6. Khairul Alam, Shinichi Takagi, and Mitsuru Takenaka, “Analysis and comparison of L valley transport in GaAs, GaSb, and Ge ultrathin-body ballistic nMOSFETs,” IEEE Transactions on Electron Devices, vol. 60(12), pp. 4213-4218, Dec. 2013.
  7. Khairul Alam and Roger Lake, “Monolayer MoS2 transistors beyond the technology roadmap,” IEEE Transactions on Electron Devices, vol. 59(12), pp. 3250-3254, Dec. 2012.
  8. Somaia Sylvia, M. Abul Khayer, Khairul Alam, and Roger Lake, “Doping, tunnel barrier, and cold carriers in InAs and InSb nanowire tunnel transistors,” IEEE Transactions on Electron Devices, vol. 59(11), pp. 2996-3001, Nov. 2012.
  9. Somaia Sylvia, Hong-Hyun Park, M. Abul Khayer, Khairul Alam, Gerhard Klimeck, and Roger Lake, “Material Selection for Minimizing Direct Tunneling in Nanowire Transistors,” IEEE Transactions on Electron Devices, vol. 59(8), pp. 2064-2069, August 2012.
  10. Khairul Alam, “Uniaxial stress modulated electronic properties of a free standing InAs nanowire,” IEEE Transactions on Electron Devices, vol. 59(3), pp. 661-665, Mar 2012.
  11. Khairul Alam and Md. Abu Abdullah, “Effects of gate dielectric constant on the performance of a gate all around InAs nanowire transistor,” IEEE Transactions on Nanotechnology, vol. 11(1), pp. 82-87, Jan 2012.
  12. Khairul Alam and Redwan N Sajjad, “Electronic properties and orientation-dependent performance of InAs nanowire transistors,” IEEE Transactions on Electron Devices, vol. 57(11), pp. 2880-2885, Nov 2010.
  13. Md. Abdul Wahab and Khairul Alam, “Performance comparison of zero-Schottky-barrier and doped contacts carbon nanotube transistors with strain applied,” Nano-Micro Letters, vol. 2(2), pp. 126-133, Jul 2010.
  14. Sishir Bhowmick and Khairul Alam, “Effects of source-drain underlaps on the performance of silicon nanowire on insulator transistors,” Nano-Micro Letters, vol. 2(2), pp. 83-88, Jun 2010.
  15. Md. Abdul Wahab and Khairul Alam, “Performance of zero-Schottky-barrier and doped contact single and double walled carbon nanotube transistors ,” Japanese Journal of Applied Physics, vol. 49(2), pp. 025101(1-6), Feb 2010.
  16. Khairul Alam, “Transport and performance of a gate all around InAs nanowire transistor,” Semiconductor Science and Technology, vol. 24(8), pp. 085003(1-6), Aug 2009.
  17. Khairul Alam, “Uniaxial strain effects on the performance of a ballistic top gate graphene nanoribbon on insulator transistor,” IEEE Transactions on Nanotechnology, vol. 8(4), pp. 528-534, Jul 2009.
  18. Redwan Sajjad, Khairul Alam, and Quazi Khosru, “Parametrization of silicon nanowire effective mass model from sp3d5s* orbital basis calculations,” Semiconductor Science and Technology, vol. 24(4), pp. 045023(1-8), Apr 2009.
  19. Redwan Sajjad and Khairul Alam, “Electronic properties of a strained <100> silicon nanowire,” Journal of Applied Physics, vol. 105(4), pp. 044307(1-6), Feb 2009.
  20. Khairul Alam, “Transport and performance of zero-Schottky barrier and doped contacts graphene nanoribbon transistors,” Semiconductor Science and Technology, vol. 24(1), pp. 015007(1-8), Jan 2009.
  21. Sishir Bhowmick and Khairul Alam, “Dielectric scaling of a top gate silicon nanowire on insulator transistor,” Journal of Applied Physics, vol. 104(12), p. 124308, Dec 2008.
  22. Khairul Alam, “Gate dielectric scaling of top gate carbon nanoribbon on insulator transistors,” Journal of Applied Physics, vol. 104(7), p. 074313, Oct 2008.
  23. Deep Shah, Nicolas Bruque, Khairul Alam, Roger Lake and Rajeev Pandey, “Electronic properties of carbon nanotubes calculated from density functional theory and the empirical p-bond model,” Journal of Computational Electronics, vol. 6(4), p. 395, Dec 2007.
  24. Khairul Alam and RogerLake, “Role of doping in carbon nanotube transistors with source/drain underlaps,” IEEE Transactions on Nanotechnology, vol. 6(6), pp. 652-658, Nov 2007.
  25. Khairul Alam and Roger Lake, “Performance metrics of a 5 nm, planar, top gate, carbon nanotube on insulator transistor,” IEEE Transactions on Nanotechnology, vol. 6(2), pp. 186-190, Mar 2007.
  26. Khairul Alam and RogerLake, “Dielectric scaling of a zero-Schottky-barrier, 5 nm gate, carbon nanotube transistor with source/drain underlaps,” Journal of Applied Physics, vol. 100, p. 024317, Jul 2006.
  27. Nicolas Bruque, Khairul Alam, Rajeev Pandey, Roger Lake, James Lewis, Xu Wang, Fei Liu, Cengiz Ozkan, Mihrimah Ozkan, and Kang Wang, “Self- assembled carbon nanotubes for electronic circuit and device applications,” Journal of Nano and Optoelectronics, vol. 1(1), p. 74, Apr 2006.
  28. Rajeev Pandey, Nocolas Bruque, Khairul Alam, and Roger Lake, “Carbon nanotube – molecular resonant tunneling diode,” Physica Status Solidi(a), vol. 203(2), p. R5, Feb 2006.
  29. Khairul Alam and Roger Lake, “Leakage and performance of zero-Schottky- barrier carbon nanotube transistors,” Journal of Applied Physics, vol. 98, p. 064307, Sep 2005.
  30. Khairul Alam and Roger Lake, “Performance of 2 nm gate length carbon nanotube field-effect transistors with source/drain underlaps,” Applied Physics Letters, vol. 87, p. 073104, Aug 2005.
  31. Yun Zheng, Cristian Rivas, Roger Lake, Khairul Alam, Timothy Boykin, and Gerhard Klimeck, “Electronic properties of silicon nanowires,” IEEE Transactions on Electron Devices, vol. 52(6), pp. 1097-1103, Jun 2005.
  32. Anisul Haque and Khairul Alam, “Accurate modeling of direct tunneling hole current in p-metal-oxide-semiconductor devices,” Applied Physics Letters, vol. 81, p. 667, (2002).
  33. Khairul Alam, Saif Zaman, Murshed Chowdhury, Rezwan Khan, and Anisul Haque, “Effects of inelastic scattering on direct tunneling gate leakage current in deep submicron metal-oxide-semiconductor transistor,” Journal of Applied Physics, vol. 92, p 937, (2002).

Conference & Seminars

  1. Khairul Alam, Shinichi Takagi, and Mitsuru Takenaka, “Thickness dependent performance of (111) GaAs UTB nMOSFETs,”16th International Workshop on Computational Electronics, June 4-7, 2013, Nara, Japan, pp. 136-137.
  2. Somaia Sarwat Sylvia, M. Abul Khayer, Khairul Alam and Roger K. Lake, “On the effect of random source doping distribution in nanowire Tunnel FETs,” TECHCON, September 9-10, 2013, Austin, Texas, USA.
  3. Somaia Sarwat Sylvia, M. Abul Khayer, Khairul Alam, Hong-Hyun Park, Gerhard Klimeck, and Roger K. Lake, “Discrete Random Distribution of Source Dopants in Nanowire Tunnel Transistors (TFETs),” APS March Meeting, Baltimore, Maryland, March 18-22, 2013.
  4. Somaia Sarwat Sylvia, Mahesh Neupane, M. Abul Khayer, Khairul Alam, and Roger K. Lake, “Material Selection for Nanowire FETs and TFETs,” 8th Annual FENA Review, Los Angeles, CA, Feb 7-8, 2012.
  5. Somaia S Sylvia, M Abul Khayer, Khairul Alam, and Roger K Lake, “Design issue analysis for InAs nanowire tunnel FETs,” Proceedings of SPIE, vol. 8102, p. 81020, Sep 2011.
  6. M. Abul Khayer, Somaia Sarwat Sylvia, Khairul Alam, and Roger K. Lake, “Effects of Heavily Doped Source on the Subthreshold Characteristics of Nanowire Tunneling Transistors,” 69th Device Research Conference, June 20-22, 2011, Santa Barbara, CA, pp. 51-52.
  7. Somaia Sarwat Sylvia, M. Abul Khayer, Khairul Alam, and Roger K. Lake, “Performance Analysis of Nanowire III-V and CNT Tunnel FETs,” 7th Annual FENA Review, Boston, MA, May 9-11, 2011.
  8. Shamim Ahmed and Khairul Alam, “Effects of phonon scattering on the performance of silicon nanowire transistors,” 6th International Conference on Electrical and Computer Engineering, December 18-20, 2010, Dhaka, Bangladesh.
  9. Sishir Bhowmick, Khairul Alam, and Quazi Khosru, “The effects of doping, gate length, and gate dielectric on inverse subthreshold slope and on/off current ratio of a top gate silicon nanowire transistor,” 5th International Conference on Electrical and Computer Engineering, December 20-22, 2008, Dhaka, Bangladesh.
  10. Redwan Sajjad, Khairul Alam, and Quazi Khosru, “Effects of uniaxial strain on the bandstructures of silicon nanowires,” 5th International Conference on Electrical and Computer Engineering, December 20-22, 2008, Dhaka, Bangladesh.
  11. Abdul Wahab and Khairul Alam, “Performance comparison of zero-Schottky- barrier single and double walled carbon nanotube transistors,” 5th International Conference on Electrical and Computer Engineering, December 20-22, 2008, Dhaka, Bangladesh.
  12. Nicolas Bruque, Rajeev Pandey, Khairul Alam, and Roger Lake, “Modeling and Design of Beyond the Roadmap Materials and Devices: Nanowires, Nanotubes, and Molecules,” International Workshop on Electron Devices and Semiconductor Technology, pp. 25-30, Tsinghua University, June 3-4, 2007.
  13. Nicolas Bruque, Rajeev Pandey, Khairul Alam, and Roger Lake, “Electron transport through molecular-carbon nanotube interfaces,” APS March Meeting, vol. 52, March 5–9, 2007, Denver, Colorado.
  14. Khairul Alam, Nicolas Bruque, and Roger Lake, “Density functional theory mode space approach applied to silicon nanowire FETs,”International Workshop on Computational Electronics, pp. 209-210, October 8-10, Amherst, USA, 2007.
  15. Rajeev Pandey, Nicolas Bruque, Khairul Alam, and Roger Lake, “Effect of CNT-amide geometry on CNT-molecular conductance,” 232nd ACS National Meeting, September 10-14, 2006, San Francisco, California, USA.
  16. Khairul Alam and RogerLake, “Near ideal operation of nanometer gate length carbon nanotube FETs,” APS March Meeting, March 21-25, 2005, Los Angeles, California, USA.
  17. Khairul Alam and RogerLake, “The effect of source/drain extension asymmetry on the leakage current of ohmicly-contacted carbon nanotube FETs,” NSTI Nanotechnology Conference, May 8-12, 2005, Anaheim, California, USA.
  18. Khairul Alam and RogerLake, “Optimal design and Coulomb blockade suppressed leakage of carbon nanotube transistors,” 63rd Annual Device Research Conference, June 20-23, 2005, Santa Barbara, California, USA.
  19. Khairul Alam, Nicolas Bruque, Rajeev Pandey, and Roger Lake, “Performance, design, and modeling of bio-assembled carbon nanotube FETs,” First International Nanotechnology Conference on Communication and Cooperation, June 2005, San Francisco, California, USA.
  20. Khairul Alam, RogerLake, and Nicolas Bruque, “High performance carbon nanotube transistors with underlap gates and Coulomb blockade suppressed leakage,” Techcon Conference, October 24-26, 2005, Portland, Oregon, USA.
  21. Yun Zheng, RogerLake, Khairul Alam, Cristian Rivas, Timothy Boykin, and Gerhard Klimeck, “Electronic properties of silicon nanowires,” 10th International Workshop on Computational Electronics (IEEE Cat. No.04EX915), 2004, pp. 82-83, Pisactaway, NJ, USA.
  22. Khairul Alam and Anisul Haque, “Modeling of hole direct tunneling gate current in pMOS devices,” 2nd International Conference on Electrical and Computer Engineering, December 26-28, 2002, pp. 76-79, Dhaka, Bangladesh.

Other

+ Academic Background

PhD in Electrical Engineering, University of California, Riverside, USA
MSc in Electrical Engineering, BUET, Bangladesh
BSc  in Electrical Engineering, BUET, Bangladesh

+ Professional Experience

August 26, 2012 – August 25, 2014 : Postdoctoral research fellow, The University of Tokyo, Japan.

June 26, 2006 – September 15, 2006 : Intern co-op, IBM T. J. Watson Research Center at Yorktown Heights, New York, USA.

September 2003 – December 2006 : Research Assistant, LAboratory for Terascale and Terahertz Electronics (LATTE), University of California, Riverside, USA.

+ Research Interest
  • Electron transport in semiconductor nanostructures
  • Strain engineering for improved performance of nano transistors
  • Photovoltaics and solar cell
  • Electronics of 2D materials
+ Selected Publications

Journal Publication

  1. Somaia S. Sylvia, Khairul Alam, and Roger Lake, Uniform Benchmarking of Low-Voltage van der Waals FETs,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 2, pp. 28-35, October 2016.
  2. Kalyan Mondol, Md. Manzurul Hasan, Yeasir Arafath, and Khairul Alam, “Quantization effects on the inversion mode of a double gate MOS,” Results in Physics, vol. 6, pp. 339-341, June 2016.
  3. Khairul Alam, Shinichi Takagi, and Mitsuru Takenaka, “A Ge ultrathin-body n-channel tunnel FET: Effects of orientation,” IEEE Transactions on Electron Devices, vol. 61(11), pp. 3594-3600, November 2014.
  4. Somaia S. Sylvia, K. M. Masum Habib, M. Abul Khayer, Khairul Alam, Mahesh Neupane, and Roger Lake, “Effects of random, discrete source dopant distribution on nanowire tunnel FETs,” IEEE Transactions on Electron Devices, vol. 61(6), pp. 2208-2214, June 2014.
  5. Khairul Alam, Shinichi Takagi, and Mitsuru Takenaka, “Strain-modulated L-valley ballistic-transport in (111) GaAs ultrathin-body nMOSFETs,” IEEE Transactions on Electron Devices, vol. 61(5), pp. 1335-1340, May 2014.
  6. Khairul Alam, Shinichi Takagi, and Mitsuru Takenaka, “Analysis and comparison of L valley transport in GaAs, GaSb, and Ge ultrathin-body ballistic nMOSFETs,” IEEE Transactions on Electron Devices, vol. 60(12), pp. 4213-4218, Dec. 2013.
  7. Khairul Alam and Roger Lake, “Monolayer MoS2 transistors beyond the technology roadmap,” IEEE Transactions on Electron Devices, vol. 59(12), pp. 3250-3254, Dec. 2012.
  8. Somaia Sylvia, M. Abul Khayer, Khairul Alam, and Roger Lake, “Doping, tunnel barrier, and cold carriers in InAs and InSb nanowire tunnel transistors,” IEEE Transactions on Electron Devices, vol. 59(11), pp. 2996-3001, Nov. 2012.
  9. Somaia Sylvia, Hong-Hyun Park, M. Abul Khayer, Khairul Alam, Gerhard Klimeck, and Roger Lake, “Material Selection for Minimizing Direct Tunneling in Nanowire Transistors,” IEEE Transactions on Electron Devices, vol. 59(8), pp. 2064-2069, August 2012.
  10. Khairul Alam, “Uniaxial stress modulated electronic properties of a free standing InAs nanowire,” IEEE Transactions on Electron Devices, vol. 59(3), pp. 661-665, Mar 2012.
  11. Khairul Alam and Md. Abu Abdullah, “Effects of gate dielectric constant on the performance of a gate all around InAs nanowire transistor,” IEEE Transactions on Nanotechnology, vol. 11(1), pp. 82-87, Jan 2012.
  12. Khairul Alam and Redwan N Sajjad, “Electronic properties and orientation-dependent performance of InAs nanowire transistors,” IEEE Transactions on Electron Devices, vol. 57(11), pp. 2880-2885, Nov 2010.
  13. Md. Abdul Wahab and Khairul Alam, “Performance comparison of zero-Schottky-barrier and doped contacts carbon nanotube transistors with strain applied,” Nano-Micro Letters, vol. 2(2), pp. 126-133, Jul 2010.
  14. Sishir Bhowmick and Khairul Alam, “Effects of source-drain underlaps on the performance of silicon nanowire on insulator transistors,” Nano-Micro Letters, vol. 2(2), pp. 83-88, Jun 2010.
  15. Md. Abdul Wahab and Khairul Alam, “Performance of zero-Schottky-barrier and doped contact single and double walled carbon nanotube transistors ,” Japanese Journal of Applied Physics, vol. 49(2), pp. 025101(1-6), Feb 2010.
  16. Khairul Alam, “Transport and performance of a gate all around InAs nanowire transistor,” Semiconductor Science and Technology, vol. 24(8), pp. 085003(1-6), Aug 2009.
  17. Khairul Alam, “Uniaxial strain effects on the performance of a ballistic top gate graphene nanoribbon on insulator transistor,” IEEE Transactions on Nanotechnology, vol. 8(4), pp. 528-534, Jul 2009.
  18. Redwan Sajjad, Khairul Alam, and Quazi Khosru, “Parametrization of silicon nanowire effective mass model from sp3d5s* orbital basis calculations,” Semiconductor Science and Technology, vol. 24(4), pp. 045023(1-8), Apr 2009.
  19. Redwan Sajjad and Khairul Alam, “Electronic properties of a strained <100> silicon nanowire,” Journal of Applied Physics, vol. 105(4), pp. 044307(1-6), Feb 2009.
  20. Khairul Alam, “Transport and performance of zero-Schottky barrier and doped contacts graphene nanoribbon transistors,” Semiconductor Science and Technology, vol. 24(1), pp. 015007(1-8), Jan 2009.
  21. Sishir Bhowmick and Khairul Alam, “Dielectric scaling of a top gate silicon nanowire on insulator transistor,” Journal of Applied Physics, vol. 104(12), p. 124308, Dec 2008.
  22. Khairul Alam, “Gate dielectric scaling of top gate carbon nanoribbon on insulator transistors,” Journal of Applied Physics, vol. 104(7), p. 074313, Oct 2008.
  23. Deep Shah, Nicolas Bruque, Khairul Alam, Roger Lake and Rajeev Pandey, “Electronic properties of carbon nanotubes calculated from density functional theory and the empirical p-bond model,” Journal of Computational Electronics, vol. 6(4), p. 395, Dec 2007.
  24. Khairul Alam and RogerLake, “Role of doping in carbon nanotube transistors with source/drain underlaps,” IEEE Transactions on Nanotechnology, vol. 6(6), pp. 652-658, Nov 2007.
  25. Khairul Alam and Roger Lake, “Performance metrics of a 5 nm, planar, top gate, carbon nanotube on insulator transistor,” IEEE Transactions on Nanotechnology, vol. 6(2), pp. 186-190, Mar 2007.
  26. Khairul Alam and RogerLake, “Dielectric scaling of a zero-Schottky-barrier, 5 nm gate, carbon nanotube transistor with source/drain underlaps,” Journal of Applied Physics, vol. 100, p. 024317, Jul 2006.
  27. Nicolas Bruque, Khairul Alam, Rajeev Pandey, Roger Lake, James Lewis, Xu Wang, Fei Liu, Cengiz Ozkan, Mihrimah Ozkan, and Kang Wang, “Self- assembled carbon nanotubes for electronic circuit and device applications,” Journal of Nano and Optoelectronics, vol. 1(1), p. 74, Apr 2006.
  28. Rajeev Pandey, Nocolas Bruque, Khairul Alam, and Roger Lake, “Carbon nanotube – molecular resonant tunneling diode,” Physica Status Solidi(a), vol. 203(2), p. R5, Feb 2006.
  29. Khairul Alam and Roger Lake, “Leakage and performance of zero-Schottky- barrier carbon nanotube transistors,” Journal of Applied Physics, vol. 98, p. 064307, Sep 2005.
  30. Khairul Alam and Roger Lake, “Performance of 2 nm gate length carbon nanotube field-effect transistors with source/drain underlaps,” Applied Physics Letters, vol. 87, p. 073104, Aug 2005.
  31. Yun Zheng, Cristian Rivas, Roger Lake, Khairul Alam, Timothy Boykin, and Gerhard Klimeck, “Electronic properties of silicon nanowires,” IEEE Transactions on Electron Devices, vol. 52(6), pp. 1097-1103, Jun 2005.
  32. Anisul Haque and Khairul Alam, “Accurate modeling of direct tunneling hole current in p-metal-oxide-semiconductor devices,” Applied Physics Letters, vol. 81, p. 667, (2002).
  33. Khairul Alam, Saif Zaman, Murshed Chowdhury, Rezwan Khan, and Anisul Haque, “Effects of inelastic scattering on direct tunneling gate leakage current in deep submicron metal-oxide-semiconductor transistor,” Journal of Applied Physics, vol. 92, p 937, (2002).

Conference & Seminars

  1. Khairul Alam, Shinichi Takagi, and Mitsuru Takenaka, “Thickness dependent performance of (111) GaAs UTB nMOSFETs,”16th International Workshop on Computational Electronics, June 4-7, 2013, Nara, Japan, pp. 136-137.
  2. Somaia Sarwat Sylvia, M. Abul Khayer, Khairul Alam and Roger K. Lake, “On the effect of random source doping distribution in nanowire Tunnel FETs,” TECHCON, September 9-10, 2013, Austin, Texas, USA.
  3. Somaia Sarwat Sylvia, M. Abul Khayer, Khairul Alam, Hong-Hyun Park, Gerhard Klimeck, and Roger K. Lake, “Discrete Random Distribution of Source Dopants in Nanowire Tunnel Transistors (TFETs),” APS March Meeting, Baltimore, Maryland, March 18-22, 2013.
  4. Somaia Sarwat Sylvia, Mahesh Neupane, M. Abul Khayer, Khairul Alam, and Roger K. Lake, “Material Selection for Nanowire FETs and TFETs,” 8th Annual FENA Review, Los Angeles, CA, Feb 7-8, 2012.
  5. Somaia S Sylvia, M Abul Khayer, Khairul Alam, and Roger K Lake, “Design issue analysis for InAs nanowire tunnel FETs,” Proceedings of SPIE, vol. 8102, p. 81020, Sep 2011.
  6. M. Abul Khayer, Somaia Sarwat Sylvia, Khairul Alam, and Roger K. Lake, “Effects of Heavily Doped Source on the Subthreshold Characteristics of Nanowire Tunneling Transistors,” 69th Device Research Conference, June 20-22, 2011, Santa Barbara, CA, pp. 51-52.
  7. Somaia Sarwat Sylvia, M. Abul Khayer, Khairul Alam, and Roger K. Lake, “Performance Analysis of Nanowire III-V and CNT Tunnel FETs,” 7th Annual FENA Review, Boston, MA, May 9-11, 2011.
  8. Shamim Ahmed and Khairul Alam, “Effects of phonon scattering on the performance of silicon nanowire transistors,” 6th International Conference on Electrical and Computer Engineering, December 18-20, 2010, Dhaka, Bangladesh.
  9. Sishir Bhowmick, Khairul Alam, and Quazi Khosru, “The effects of doping, gate length, and gate dielectric on inverse subthreshold slope and on/off current ratio of a top gate silicon nanowire transistor,” 5th International Conference on Electrical and Computer Engineering, December 20-22, 2008, Dhaka, Bangladesh.
  10. Redwan Sajjad, Khairul Alam, and Quazi Khosru, “Effects of uniaxial strain on the bandstructures of silicon nanowires,” 5th International Conference on Electrical and Computer Engineering, December 20-22, 2008, Dhaka, Bangladesh.
  11. Abdul Wahab and Khairul Alam, “Performance comparison of zero-Schottky- barrier single and double walled carbon nanotube transistors,” 5th International Conference on Electrical and Computer Engineering, December 20-22, 2008, Dhaka, Bangladesh.
  12. Nicolas Bruque, Rajeev Pandey, Khairul Alam, and Roger Lake, “Modeling and Design of Beyond the Roadmap Materials and Devices: Nanowires, Nanotubes, and Molecules,” International Workshop on Electron Devices and Semiconductor Technology, pp. 25-30, Tsinghua University, June 3-4, 2007.
  13. Nicolas Bruque, Rajeev Pandey, Khairul Alam, and Roger Lake, “Electron transport through molecular-carbon nanotube interfaces,” APS March Meeting, vol. 52, March 5–9, 2007, Denver, Colorado.
  14. Khairul Alam, Nicolas Bruque, and Roger Lake, “Density functional theory mode space approach applied to silicon nanowire FETs,”International Workshop on Computational Electronics, pp. 209-210, October 8-10, Amherst, USA, 2007.
  15. Rajeev Pandey, Nicolas Bruque, Khairul Alam, and Roger Lake, “Effect of CNT-amide geometry on CNT-molecular conductance,” 232nd ACS National Meeting, September 10-14, 2006, San Francisco, California, USA.
  16. Khairul Alam and RogerLake, “Near ideal operation of nanometer gate length carbon nanotube FETs,” APS March Meeting, March 21-25, 2005, Los Angeles, California, USA.
  17. Khairul Alam and RogerLake, “The effect of source/drain extension asymmetry on the leakage current of ohmicly-contacted carbon nanotube FETs,” NSTI Nanotechnology Conference, May 8-12, 2005, Anaheim, California, USA.
  18. Khairul Alam and RogerLake, “Optimal design and Coulomb blockade suppressed leakage of carbon nanotube transistors,” 63rd Annual Device Research Conference, June 20-23, 2005, Santa Barbara, California, USA.
  19. Khairul Alam, Nicolas Bruque, Rajeev Pandey, and Roger Lake, “Performance, design, and modeling of bio-assembled carbon nanotube FETs,” First International Nanotechnology Conference on Communication and Cooperation, June 2005, San Francisco, California, USA.
  20. Khairul Alam, RogerLake, and Nicolas Bruque, “High performance carbon nanotube transistors with underlap gates and Coulomb blockade suppressed leakage,” Techcon Conference, October 24-26, 2005, Portland, Oregon, USA.
  21. Yun Zheng, RogerLake, Khairul Alam, Cristian Rivas, Timothy Boykin, and Gerhard Klimeck, “Electronic properties of silicon nanowires,” 10th International Workshop on Computational Electronics (IEEE Cat. No.04EX915), 2004, pp. 82-83, Pisactaway, NJ, USA.
  22. Khairul Alam and Anisul Haque, “Modeling of hole direct tunneling gate current in pMOS devices,” 2nd International Conference on Electrical and Computer Engineering, December 26-28, 2002, pp. 76-79, Dhaka, Bangladesh.

Other